Non-volatile memories are susceptible to data retention degradation caused by, for example, intrinsic charge loss (ICL) and stress-induced leakage (SILC). The term “data retention degradation” herein refers to corruption or toss of data in the non-volatile memory. It also refers to reduction in retention time limit associated with the non-volatile memory. Data retention degradation is exacerbated as the number of program erase cycles increase. The term “program erase cycles” refers to periods of time when data in the non-volatile memory is deleted or replaced with new data.
Data retention degradation is also exacerbated with heavy usage of the non-volatile memory e.g., sequences of high work loads followed by time periods when the non-volatile memory is idle and retaining data. During the time the non-volatile memory is idle, the data in the non-volatile memory can only be obtained for a finite amount of time. The term “idle” herein refers to duration when a data location in the non-volatile memory is written with data and before the data location is re-written with new data or erased. This finite amount of time beyond which data in the idle non-volatile memory corrupts or is lost is referred to herein as “retention time limit.”
The data loss caused by data retention degradation results in unacceptably high uncorrectable bit error rate. System level solutions to resolve data retention degradation, such as wear-leveling, require complicated logic units to reduce the number of program-erase cycles that any block of the non-volatile memory experiences for a given workload. However, with wear-leveling the non-volatile memory may continue to experience a fixed number of program erase cycles per data location.